The present invention relates to a semiconductor device; and, more particularly, to a metal oxide semiconductor (MOS) transistor capable of preventing a saturation current variation.
Generally, a saturation current generated between a source and a drain of a metal oxide semiconductor (MOS) transistor is varied due to a temperature variation. That is, characteristics of an integrated circuit, such as a constant voltage generation circuit or a delay circuit, including the MOS transistor are changed due to the temperature variation. If the characteristics of the integrated circuit are excessively changed based on predetermined conditions such as temperature and pressure, the integrated circuit may not be normally operated.
Accordingly, during manufacturing steps, integrated circuits are tested at a severe temperature, e.g., −10° C. or 90° C., in order to screen out a defective circuit. Since the defective circuit cannot be used by users, it is desirable to produce a MOS transistor stably operated regardless of the temperature variation.
FIG. 1 is a schematic circuit diagram showing a conventional constant voltage generation circuit including conventional MOS transistors.
As shown, the conventional constant voltage generation circuit includes a first and a second n-type metal oxide semiconductor (NMOS) transistors M1 and M2; a first and a second p-type metal oxide semiconductor (PMOS) transistors M3 and M4; and a resistor R.
A source of the second NMOS transistor M2 is coupled to a ground GND. A gate of the second NMOS transistor M2 is coupled to a gate of the first NMOS transistor M1. The gate of the first NMOS transistor M1 is also coupled to a drain of the first NMOS transistor M1. A source of the first NMOS transistor M1 is coupled to a first terminal of the resistor R and a second terminal of the resistor R is connected to the ground GND.
Each source of the first PMOS transistor M3 and the second PMOS transistor M4 is connected to a power supply voltage VCC. Each gate of the first PMOS transistor M3 and the second PMOS transistor M4 is coupled to each other. A drain of the first PMOS transistor M3 and a drain of the second PMOS transistor M4 are respectively coupled to the drain of the first NMOS transistor M1 and the drain of the second NMOS transistor M4.
The first and the second PMOS transistors M3 and M4 are served as a current mirror circuit for operating the first and the second NMOS transistors M1 and M2. The MOS transistors M1 to M4 shown in FIG. 1 are served as a Widlar-type current mirror circuit for generating a constant voltage VR0.
Herein, it is noted that the resistor R is connected between the first NMOS transistor M1 and the ground GND. A role of the resistor R is described below.
FIG. 2 is a lay-out of each MOS transistor, e.g., M1, included in the conventional constant voltage generation circuit shown in FIG. 1.
As shown, the first NMOS transistor M1 includes a gate line 201, a source region 202 and a drain region 203.
Each of the source region 202 and the drain region 203 includes a plurality of contacts, e.g., a contact 204 included in the source region 202 and a contact 205 included in the drain region 203, for supplying a power and connecting internal elements. The gate line 201 also includes contacts, e.g., 206. Herein, it is noted that the number of contacts included in the source region 202 is same to the number of contacts included in the drain region 203.
Further, a size of the first NMOS transistor M1 is determined by a ratio of width to length. The length corresponds to a distance between the source region 202 and the drain region 203, and the width corresponds to a length of a tangent line between the gate line 201 and the source region 202 or the drain region 203.
Meanwhile, as above-mentioned, a saturation current of a conventional MOS transistor having a structure such as the lay-out shown in FIG. 2 can be abnormally changed due to the unstable temperature. Accordingly, the conventional constant voltage generation circuit having the conventional MOS transistor can operate abnormally.
Therefore, for compensating the change of the performance of the above constant voltage generation circuit, it is necessary that the resistor R is connected between the first NMOS transistor M1 and the ground GND. That is, for reducing the change of the characteristics caused by the temperature variation, the resistance of the resistor R and the size of the first NMOS transistor M1 are appropriately adjusted.